Hardware Description Languages

What is an HDL? 

HDL(Hardware Description Language):- A hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. It can describe the circuit's operation, its design, and tests to verify its operation by means of simulation.

HDL’s are used to write specifications of some piece of hardware.

HDL specifies a model for the expected behaviour of a circuit before that circuit is designed and built. The end result is a silicon chip that would be manufactured in a fab.

A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is physically created.

HDL’s find applications in Programmable Logic Devices (PLD’s) - simple PLD’s to complex PLD’s like CPLD (Complex Programmable Gate Array), FPGA (Field Programmable Gate Array) etc.

HDLs in use today – ABEL, PALASM, CUPL for less complex devices;  VHDL, Verilog for larger CPLD & FPGA devices.

Two applications of HDL processing: Simulation and Synthesis.

Thanks to Moore’s Law, the number of programmable logic gates (e.g. AND gates, NAND gates, etc) in today’s chips are now in the millions.

With such electronic capacities on a single chip, it is now possible to place whole electronic systems on a chip.

Using HDL’s it is almost as easy to program hardware as to program software. But, one needs to understand the principles of digital electronic design (e.g. multiplexer’s, flip-flop’s, buffer’s, counter’s, etc).

Why simulate first?

Physical bread-boarding is not possible as designs reach higher levels of integration.

A simulator interprets the HDL description and produces a readable output, such as a timing diagram, that predicts how the hardware will behave before it is actually fabricated.

Simulation allows the detection of functional errors in a design without having to physically create the circuit.

Logic Simulation

The stimulus that tests the functionality of the design is called a test bench.

To simulate, the design is first described in HDL, verified by simulating the design and checking it with a test bench which is also written in HDL.

Logic simulation is a fast, accurate method of analyzing a circuit by checking functionality using waveforms

HDL’s in demand today

Two standard HDL’s that are supported by IEEE.

• VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) – Sometimes referred to as VHSIC HDL, this was developed from an initiative by US. Dept. of Defense.
  
• Verilog HDL – developed by Cadence Design Systems and later transferred to a consortium called Open Verilog International (OVI).