1. What is the output of AND gate in the circuit below, when A and B are as in waveform? Tp is the gate delay of respective gate.
2. Identify the circuit below, and its limitation.
3. What is the current through the resistor R1 (Ic) ?
4. Referring to the diagram below, briefly explain what will happen if the propagation delay of the clock signal in path B is much too high compared to path A. How do we solve this problem if the propagation delay in path B can not be reduced ?
5. What is the function of a D flip-flop, whose inverted output is connected to its input ?
6. Design a circuit to divide input frequency by 2.
7. Design a divide-by-3 sequential circuit with 50% duty cycle.
8. Design a divide-by-5 sequential circuit with 50% duty cycle.
9. What are the different types of adder implementations ?
10. Draw a Transmission Gate-based D-Latch.
11. Give the truth table for a Half Adder. Give a gate level implementation of it.
12. What is the purpose of the buffer in the circuit below, is it necessary/redundant to have a buffer ?
13. What is the output of the circuit below, assuming that value of 'X' is not known ?
14. Consider a circular disk as shown in the figure below with two sensors mounted X, Y and a blue shade painted on the disk for an angle of 45 degree. Design a circuit with minimum number of gates to detect the direction of rotation.
15. Design an OR gate from 2:1 MUX.
16. Design an XOR gate from 2:1 MUX and a NOT gate
17. What is the difference between a LATCH and a FLIP-FLOP ?
- Latch is a level sensitive device while flip-flop is an edge sensitive device.
- Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
- Latches take less gates (also less power) to implement than flip-flops.
- Latches are faster than flip-flops.
18. How can you generate random sequences in digital circuits?
19. Design a D Flip-Flop from two latches.
20. Design a 2 bit counter using D Flip-Flop.
21. What are the two types of delays in any digital system ?
22. Design a Transparent Latch using a 2:1 Mux.
23. Design a 4:1 Mux using 2:1 Muxes and some combo logic.
24. What is metastable state ? How does it occur ?
25. What is metastability ?
26. Design a 3:8 decoder
27. Design a FSM to detect sequence "101" in input sequence.
28. Convert NAND gate into Inverter, in two different ways.
29. Design a D and T flip flop using 2:1 mux; use of other components not allowed, just the mux.
30. Design a divide by two counter using D-Latch.
31. Design D Latch from SR flip-flop.
32. Define Clock Skew , Negative Clock Skew, Positive Clock Skew.
33. What is Race Condition ?
34. Design a 4 bit Gray Counter.
35. Design 4-bit Synchronous counter, Asynchronous counter.
36. Design a 16 byte Asynchronous FIFO.
37. What is the difference between an EEPROM and a FLASH ?
38. What is the difference between a NAND-based Flash and a NOR-based Flash ?
39. You are given a 100 MHz clock. Design a 33.3 MHz clock with and without 50% duty cycle.
40. Design a Read on Reset System ?
41. Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.
42. Design a State machine for Traffic Control at a Four point Junction.
43. What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to make it asynchronous FIFO ?