AICTE SPONSORED
STAFF DEVELOPMENT PROGRAMME
ON
NANOELECTRONICS
10th to 21st May, 2010
Organized by
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING &
CENTRE FOR CONTINUING EDUCATION
CENTRE FOR CONTINUING EDUCATION
NATIONAL INSTITUTE OF TECHNOLOGY CALICUT
(A Deemed University under Govt.of India)
NIT Campus P.O. CALICUT, 673601.Kerala, India
Preamble
The ever-increasing demand for higher processing speeds inevitably leads to an increased density of gates in an IC. Coupled with the increasing switching speed is the problem of increased power dissipation. Also, the conventional MOS device, which is the workhorse of VLSI technology, behaves different for smaller dimensions compared to its larger cousin. New design constraints come up dictated by increased gate leakage, tunneling and the interconnects. These have led to different device configurations and geometries. Multiple gate MOSFETs, vertical MOSFETs, FinFETs, Silicon-on-insulator, strained Si devices are some of the widely used extensions of the basic MOSFET. An alternate strategy is to employ tunneling to obtain large speeds. The resonant tunneling devices have tunneling at their very roots. Such devices are possible due to heterostructures. Si- Ge heterostructures and those formed by GaAs and its alloys are widely employed for high speeds. Yet another alternative is to do away with semiconductors and use insulators and metals. This strategy is employed in the single electron transistor. Many other technologies based on organic molecules particularly the bucky balls have been proposed. The tremendous potential of the field of nanoelectronics is expected to change the way we do computing and signal processing in a fundamentally different and profound manner.
Course Content
- Design methodology in ultra deep sub-micron regime
- CMOS Scaling: Issues for sub 45 nm node
Technologies
- Alternate device structures
- Heterostructures
- Resonant tunneling devices
- Single electron transistors
- Carbon Nano Tube FET
Speakers
- Eminent persons from academia and industry
Eligibility
The course is open to teachers from AICTE approved Engineering Colleges/Polytechnics with a basic qualification in electronics.
Registration Fee
Registration fee is Rs. 500 (is refundable only if not selected/ selected and participated). The registration fee shall be paid through a crossed demand draft, drawn in favor of “Coordinator, Nano electronics” payable at State Bank of India, REC Chathamangalam Branch (Code 2207).
Travel
Participants will be reimbursed travel expenses limited to sleeper class train fare by the shortest route as per NIT Calicut norms.
Fore more info click here
