I2C Serial Protocol

• Serial communication protocols
• Meant for short distances “inside the box”
• Low complexity
• Low cost
• Low speed ( a few Mbps at the fastest )
• To be discussed: Applications, protocols, tradeoffs, AVR support

What is I2C?

• Shorthand for an “Inter-integrated circuit” bus
• Developed by Philips Semiconductor for TV sets in the 1980’s
• I2C devices include EEPROMs, thermal sensors, and real-time clocks
• Used as a control interface to signal processing devices that have separate data interfaces, e.g. RF tuners, video decoders and encoders, and audio processors.
• I2C bus has three speeds:

...............................Slow (under 100 Kbps)
...............................Fast (400 Kbps)
...............................High-speed (3.4 Mbps) – I2C v.2.0

• Limited to about 10 feet for moderate speeds

I2C Bus Configuration

• 2-wire serial bus – Serial data (SDA) and Serial clock (SCL)
• Half-duplex, synchronous, multi-master bus
• No chip select or arbitration logic required
• Lines pulled high via resistors, pulled down via open-drain drivers (wired-AND)

I2C Protocol

• Master sends start condition (S) and controls the clock signal
• Master sends a unique 7-bit slave device address
• Master sends read/write bit (R/W) – 0 - slave receive, 1 - slave transmit
• Receiver sends acknowledge bit (ACK)
• Transmitter (slave or master) transmits 1 byte of data
• Receiver issues an ACK bit for the byte received
• Repeat 5 and 6 if more bytes need to be transmitted.
• a)For write transaction (master transmitting), master issues stop condition (P) after last byte of data.
  b)For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the slave the transmission is done
  
  

I2C Signals

• Start – high-to-low transition of the SDA line while SCL line is high
• Stop – low-to-high transition of the SDA line while SCL line is high
• Ack – receiver pulls SDA low while transmitter allows it to float high
• Data – transition takes place while SCL is slow, valid while SCL is high

I2C Features

• “Clock stretching” – when the slave (receiver) needs more time to process a bit, it can pull SCL low. The master waits until the slave has released SCL before sending the next bit.
• “General call” broadcast – addresses every device on the bus
• 10-bit extended addressing for new designs. 7-bit addresses all exhausted

Advantages:

• Good for communication with on-board devices that are accessed occasionally.
• Easy to link multiple devices because of addressing scheme
• Cost and complexity do not scale up with the number of devices

Disadvantages:

• The complexity of supporting software components can be higher than that of competing schemes ( for example, SPI ).
• Shorthand for “Serial Peripheral Interface”
• Defined by Motorola on the MC68HCxx line of microcontrollers
• Generally faster than I2C, capable of several Mbps