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Showing posts with label Basic IC Processing Steps. Show all posts
Showing posts with label Basic IC Processing Steps. Show all posts

Intel shows how a CPU is manufactured




Sand. Made up of 25 percent silicon, is, after oxygen, the second most abundant chemical element that's in the earth's crust. Sand, especially quartz, has high percentages of silicon in the form of silicon dioxide (SiO2) and is the base ingredient for semiconductor manufacturing.






After procuring raw sand and separating the silicon, the excess material is disposed of and the silicon is purified in multiple steps to finally reach semiconductor manufacturing quality which is called electronic grade silicon. The resulting purity is so great that electronic grade silicon may only have one alien atom for every one billion silicon atoms. After the purification process, the silicon enters the melting phase. In this picture you can see how one big crystal is grown from the purified silicon melt. The resulting mono-crystal is called an ingot.




A mono-crystal ingot is produced from electronic grade silicon. One ingot weighs approximately 100 kilograms (or 220 pounds) and has a silicon purity of 99.9999 percent.




The ingot is then moved onto the slicing phase where individual silicon discs, called wafers, are sliced thin. Some ingots can stand higher than five feet. Several different diameters of ingots exist depending on the required wafer size. Today, CPUs are commonly made on 300 mm wafers.




Once cut, the wafers are polished until they have flawless, mirror-smooth surfaces. Intel doesn't produce its own ingots and wafers, and instead purchases manufacturing-ready wafers from third-party companies. Intel’s advanced 45 nm High-K/Metal Gate process uses wafers with a diameter of 300 mm (or 12-inches). When Intel first began making chips, it printed circuits on 50 mm (2-inches) wafers. These days, Intel uses 300 mm wafers, resulting in decreased costs per chip.




The blue liquid, depicted above, is a photo resist finish similar to those used in film for photography. The wafer spins during this step to allow an evenly-distributed coating that's smooth and also very thin.




At this stage, the photo-resistant finish is exposed to ultra violet (UV) light. The chemical reaction triggered by the UV light is similar to what happens to film material in a camera the moment you press the shutter button.

Areas of the resist on the wafer that have been exposed to UV light will become soluble. The exposure is done using masks that act like stencils. When used with UV light, masks create the various circuit patterns. The building of a CPU essentially repeats this process over and over until multiple layers are stacked on top of each other.

A lens (middle) reduces the mask's image to a small focal point. The resulting "print" on the wafer is typically four times smaller, linearly, than the mask's pattern.




In the picture we have a representation of what a single transistor would appear like if we could see it with the naked eye. A transistor acts as a switch, controlling the flow of electrical current in a computer chip. Intel researchers have developed transistors so small that they claim roughly 30 million of them could fit on the head of a pin.




After being exposed to UV light, the exposed blue photo resist areas are completely dissolved by a solvent. This reveals a pattern of photo resist made by the mask. The beginnings of transistors, interconnects, and other electrical contacts begin to grow from this point.




The photo resist layer protects wafer material that should not be etched away. Areas that were exposed will be etched away with chemicals.




After the etching, the photo resist is removed and the desired shape becomes visible.




More photo resist (blue) is applied and then re-exposed to UV light. Exposed photo resist is then washed off again before the next step, which is called ion doping. This is the step where ion particles are exposed to the wafer, allowing the silicon to change its chemical properties in a way that allows the CPU to control the flow of electricity.




Through a process called ion implantation (one form of a process called doping) the exposed areas of the silicon wafer are bombarded with ions. Ions are implanted in the silicon wafer to alter the way silicon?i these areas conduct electricity. Ions are propelled onto the surface of the wafer at very high velocities. An electrical field accelerates the ions to a speed of over 300,000 km/hour (roughly 185,000 mph)




After the ion implantation, the photo resist will be removed and the material that should have been doped (green) now has alien atoms implanted.




This transistor is close to being finished. Three holes have been etched into the insulation layer (magenta color) above the transistor. These three holes will be filled with copper, which will make up the connections to other transistors.




The wafers are put into a copper sulphate solution at this stage. Copper ions are deposited onto the transistor through a process called electroplating. The copper ions travel from the positive terminal (anode) to the negative terminal (cathode) which is represented by the wafer.




The copper ions settle as a thin layer on the wafer surface.




The excess material is polished off leaving a very thin layer of copper.




Multiple metal layers are created to interconnects (think wires) in between the various transistors. How these connections have to be “wired” is determined by the architecture and design teams that develop the functionality of the respective processor (for example, Intel’s Core i7 processor). While computer chips look extremely flat, they may actually have over 20 layers to form complex circuitry. If you look at a magnified view of a chip, you will see an intricate network of circuit lines and transistors that look like a futuristic, multi-layered highway system.

This fraction of a ready wafer is being put through a first functionality test. In this stage test patterns are fed into every single chip and the response from the chip monitored and compared to "the right answer."




After tests determine that the wafer has a good yield of functioning processor units, the wafer is cut into pieces (called dies).




The dies that responded with the right answer to the test pattern will be put forward for the next step (packaging). Bad dies are discarded. Several years ago, Intel made key chains out of bad CPU dies.




This is an individual die, which has been cut out in the previous step (slicing). The die shown here is a die of an Intel Core i7 processor.




The substrate, the die, and the heatspreader are put together to form a completed processor. The green substrate builds the electrical and mechanical interface for the processor to interact with the rest of the PC system. The silver heatspreader is a thermal interface where a cooling solution will be applied. This will keep the processor cool during operation.




A microprocessor is the most complex manufactured product on earth. In fact, it takes hundreds of steps and only the most important ones have been visualized in this picture story.




During this final test the processors will be tested for their key characteristics (among the tested characteristics are power dissipation and maximum frequency).




Based on the test result of class testing processors with the same capabilities are put into the same transporting trays. This process is called "binning". Binning determines the maximum operating frequency of a processor, and batches are divided and sold according to stable specifications.




The manufactured and tested processors (again Intel Core i7 processor is shown here) either go to system manufacturers in trays or into retail stores in a box. Many thanks to Intel for supplying the text and photos in this picture story. Check out Intel's site for full size images of this entire process.
 

CHEMICAL VAPOUR DEPOSITION

  • Deposition of a solid material onto a heated substrate via decomposition or channel reaction of compounds contained in the gas passing over the substrate
  • Many materials such as silicon nitride silicon dioxide ,polycrystalline silicon silicon ,and single crystal silicon ,can be deposited via CVD
  • Aspecial case of CVD is called epitaxy or epitaxial layer deposition or vapour phase epitaxy(VPE) , in which case the deposited layer is in single crystal form
  • In CVD process the materials to be deposited enter a reaction chamber in the gaseous or vapour phase and react on or near the surface of the substrates ,which are at some elevated temperatures
  • The chemical reaction that occurs produces the atoms or molecules that are deposited on the substrate surface
A number of different materials can be deposited by the CVD process
  1. Silicon epitaxial layer on a single-crystal silicon substrate
  2. Silicon epitaxial layer deposition on a sapphire
  3. Silicon dioxide deposition
  4. Silicon nitride deposition

EPITAXIAL DEPOSITION


  • The word “epitaxy” is a Greek word ‘epi’ means ‘upon’ and ‘taxy’ means ‘arranged’
  • ie, it is an arrangement of atoms upon a crystal substrate ,so that the resulting added layer structure is an exact extension of the crystal structure
  • There are a number of different chemical reactions that can be used for the deposition of epitaxial layers
Four silicon sources have been used for growing epitaxial silicon–
Silicontetra chloride(SiCl4), dichlorosilane(SiH2Cl2),trichlorosilane(SiHCl3) and silane(SiH4)

Some important Reactions for Epitaxial layer Deposition



  • Silicon tetrachloride has been the most studied and has seen the widest industrial use.The overall reaction can be classed as a hydrogen reduction of a gas
SiCl4(gas) + 2H2(gas) --> Si(solid)+4HCl(gas)
  • The epitaxial layer deposition takes place in a chamber called an epitaxial reactor
  • Horizontal reactor ,Vertical reactor, Cylindrical reactor
  • Horizontal reactors offer lowest cost construction,however controlling the deposition process over the entire susceptor length is a problem
  • Vertical reactors are capable of very uniform deposition, but suffer from mechanical complexity
  • Cylindrical reactors are also capable of uniform deposition due to employment of radiant heating,but are not suited for extended operation at temperature above 1200c

  • The process is carried out in a reaction chamber consisting of a long cylindrical quartz tube encircled by an RF induction coil
  • The silicon wafers are placed on a rectangular graphite rod called a boat
  • This boat is then placed in the reaction chamber where the graphite is heated inductively to a temperature 1200c
  • The various gases required for the growth of desired epitaxial layers are introduced into the system through a control console
  • The basic chemical reaction used for the epitaxial growth of pure silicon is the hydrogen reduction of silicon tetrachloride
SiCl4+2H2 <--> Si+4HCl
  • For producing doped p or n type epitaxial layers, a number of gases can be metered into the reactor tube, including some very small amounts of doping gases,such as B2H6(diborane) for boron doping and PH3(Phosphine) for phosphorous doping of the epitaxial layer

Advantages

  • SiCl4 is non-toxic,inexpensive and easy to purify
  • The reaction making silicon from SiCl4 takes place only at surface and not on the boat or reaction chamber walls

Disadvantages

  • The growth process is accompanied by the diffusion phenomenon which causes an exchange of impurities between silicon wafer and growing film.This prevents the fabrication of an ideal step junction
  • SiCl4 process requires higher temperature and also has slower growth rate

Ion Implantation




  • Technique used to introduce impurities into a silicon wafer
  • Silicon wafers are placed in a vaccum chamber and are scanned by a beam of high energy dopant ions(borons for p-type and phosphorous for n-type)
  • These ions are accelerated by energies between 20kv to 250 kv
  • As the ions strike the silicon wafers ,they penetrate some small distance into the wafer
  • The depth of penetration of any particular type of ion increases with increasing accelerating voltage


Properties of ion implantation


  • The depth of penetration of any particular type of ion will increase with increasing accelerating voltage
  • The penetration depth will generally be in the range of .1 to 1µm

Range distributions


Impurity Distribution of implanted ions:- The distribution of the implanted ions as a function of distance x from the silicon surface will be a Gaussian distribution ,given by

N(x)=Npexp[-(x-Rp)² /2ΔRp²]
x=distance into substrate from surface
Rp=projected range
ΔRp=standard deviation of the projected range
Np=peak concentration of implanted ions


An ion implantation impurity profile




The peak implanted ion concentration is related to the implantation dosage Q by
Np= Q/(2π)½ΔRp =.4[Q/ΔRp]
  • The implantation dosage Q is the number of implanted ions per unit of surface area as given by such units as ions/cm2.
  • The ion density drops off rapidly from the peak value with distance as measured from Rp in either direction

Annealing after implantation


  • After the ions have been implanted they are lodged principally in interstitial positions in the silicon crystal structure and the surface region into which the implantation has taken place will be heavily damaged by the impact of the high energy ions
  • The disarray of silicon atoms in the surface region is often to the extent that this region is no longer crystalline in structure but ,rather amorphous
  • To restore this surface region back to well-ordered crystalline state and to allow the implanted ions to go into substitutional sites in the crystal structure , the wafer must be subjected to an annealing process
  • The annealing process usually involves the heating of the wafers to some elevated temperature often in the range of 1000c for a suitable length of time such as 30 minutes
  • Laser beam and electron beam annealing are also employed. In such annealing techniques only the surface region of the wafer is heated and recrystallized

Advantages

  • Provides much more precise control over the density of dopants(Q) deposited into the wafer,and hence the sheet resistanse.
  • In diffusion process, temperature has to be controlled over a large area inside the oven,whereas in ion implantation technique, accelerating potential and the beam current are electrically controlled from outside
  • Possible to have very low values of dosage(Q) ,so that very large values of sheet resistance can be obtained
  • Performed at low temperatures